The present disclosure relates generally to semiconductor fabrication, and more particularly, to semiconductor fabrication process control.
As performance requirements and throughput demands increase, semiconductor fabrication process control has become even more crucial. However, as process geometries decrease, such as from 65 to 45 nanometer and beyond, it may be challenging to keep process variations at acceptable levels. As such, the processes may suffer from losses in tool productivity, increased operator interaction, yield loss, and higher rework rates, all possibly leading to higher costs. Advanced Process Control (APC), which may consist of models and feedback systems among other process control techniques, has been widely used to help alleviate some of the variations. However sufficient APC methods may be lacking, especially during the initial processing of a new chip design. Traditionally, when a new design needs to be implemented on a wafer, the pilot processing run may require three or more feedback cycles before a quality parameter, such as critical dimension uniformity, is within tolerance (each cycle corresponding to a patterned test wafer). These cycles are time consuming and each additional cycle may add approximately one and a half days to the pilot run time. One reason pilot runs require multiple cycles is because the optimal semiconductor processing parameters are unknown on the initial cycle. Moreover, processing feedback is not available until after the first cycle. Consequently, although existing APC techniques have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.